CIRCUIT PORTFOLIO

From specification.
To physical design.

10 circuit designs developed with AI-assisted workflows, from analog blocks to full-chip integration. Explore layouts, simulation results and technology-specific verification.

FULL-CHIP INTEGRATION

AiSIC mixed-signal test chip

A 65-nm mixed-signal test chip for laser fault-injection research, bringing together analog instrumentation, sensing structures and a RISC-V digital subsystem. Its development combines AI-assisted design and integration with human engineering direction.

65 nm CMOS · 1 × 1 mm die · 21 blocks · 32 pads

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Data conversion

SAiR10 SAR ADC

A 10-bit, 5-MS/s asynchronous SAR ADC taken from a common specification to three technology-specific layouts.

65 nm CMOS · 22 nm FD-SOI · 16 nm FinFET

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Analog building block

Eight-output bias generator

A wide-swing cascode mirror distributing matched 10-µA currents, redesigned and checked for each process.

65 nm CMOS · 22 nm FD-SOI · 16 nm FinFET

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Analog building block

Untrimmed current reference

A temperature-compensated 10-µA reference whose architecture was tested across bulk CMOS, FD-SOI and FinFET.

65 nm CMOS · 22 nm FD-SOI · 16 nm FinFET

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Analog building block

PTAT temperature sensor

A switched-current ΔVBE sensor across bulk CMOS, FD-SOI and FinFET, with signed-off layouts and complete temperature, noise and Monte Carlo characterization.

65 nm CMOS · 22 nm FD-SOI · 16 nm FinFET

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Analog building block

Frequency-to-voltage converter

A switched-capacitor monitor turning clock-frequency shifts into a live analog readout, across bulk CMOS, FD-SOI and FinFET.

65 nm CMOS · 22 nm FD-SOI · 16 nm FinFET

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Analog building block

Monitor buffer

A rail-to-rail unity-gain amplifier driving the pad, board and scope load. Explore performance tables and 13 characterization figures from retained sign-off data, with technology coverage identified per plot.

65 nm CMOS · 22 nm FD-SOI · 16 nm FinFET

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Analog building block

Period-to-voltage converter

A fast converter migrated from 180 nm to 65 nm CMOS, with 2-bit gain control centred at 500 MHz or 1 GHz and an output buffer for the pad.

65 nm bulk CMOS · 675 µm²

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Laser-capture front end

Analog front end

Three sensing paths with programmable transimpedance gain, matched response and on-chip electrical calibration.

65 nm bulk CMOS · Layout and technical results

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Transient waveform capture

Sampled capture array

A 61-cell single-shot capture array with an equivalent-time mode, programmable timing and calibrated readout.

65 nm bulk CMOS · Layout and technical results

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These designs include physical layouts and simulation results. Each page states its verification status, operating conditions and remaining checks; results are not measured-silicon data.

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