TRAME / AI-DRIVEN IC DESIGN

A complete chip.
From spec to tape-out.

AI-driven design. Human expertise. Follow a complete design journey, with engineers in control.

Local PDK AI-Agent · Designed for NDA-governed workflows How it works

Based on the published case studies.

HOW TRAME WORKS

Design with AI.
Decide with expertise.

Trame AI-Agent connects the work. Your engineers set the requirements, review the evidence and approve the next step.

  1. 01

    Define

    Specifications, technology and rules.

  2. 02

    Design

    Circuits, models and testbenches.

  3. 03

    Implement

    Layout, routing and integration.

  4. 04

    Verify

    Simulation, PVT, Monte Carlo and PEX.

  5. 05

    Sign off

    Verification closure and engineer-approved release.

LOCAL PDK AI-AGENT

Your PDK.
Your confidential environment.

The PDK AI-Agent runs locally, alongside your proprietary models, libraries and design rules.

Designed to support foundry NDA requirements, with technology-aware reasoning inside your authorised environment.

  • Local processingPDK analysis, simulation and optimisation within your environment.
  • Controlled disclosureGateway policy: approved design requests and abstract results only.
  • Your access policiesModel routing and disclosure rules are agreed against your NDA and licence terms before deployment.
Discuss your confidentiality requirements
GLOBAL ORCHESTRATIONTrame AI Core

Reasoning · Circuit design
Planning · Orchestration

Design requests
Approved abstract results

LOCAL ENVIRONMENT · CONFIDENTIAL
Communication gateway

Access control · Disclosure policies

TRAME AI EDGELocal PDK AI-Agent

Technology-aware reasoning
Simulation analysis · Optimisation

EDA engines

SPICE · Synthesis · Layout
DRC · LVS · PEX

Proprietary PDKs

Models · Libraries
Design rules

Local PDK deployment architecture. Data-sharing permissions are defined for each deployment.

DESIGNED WITH TRAME

Start with a circuit.
See how it was built.

All 10 circuit designs
PTAT temperature-sensor layouts in three technologies at one scale

Analog building block

PTAT temperature sensor

A switched-current ΔVBE sensor across bulk CMOS, FD-SOI and FinFET, with signed-off layouts and complete temperature, noise and Monte Carlo characterization.

65 nm CMOS · 22 nm FD-SOI · 16 nm FinFET

Explore this circuit
Analog front end layout in 65 nm bulk CMOS with a 10 µm scale bar

Laser-capture front end

Analog front end

Three sensing paths with programmable transimpedance gain, matched response and on-chip electrical calibration.

65 nm bulk CMOS · Layout and technical results

Explore this circuit

Explore physical layouts, simulation curves and verification scope. Each design includes its simulation conditions and verification status.

WORK WITH THE TOOLS YOU USE

Your tools.
Your design workflow.

Trame EDA. Cadence. Synopsys. Siemens EDA.

Start with your current environment. We define the exact products, versions, interfaces and workflow steps covered by the engagement.

YOUR EXISTING ENVIRONMENT

Build on your Cadence workflow.

Connect Trame to your Cadence design, simulation and verification workflows. Deployment defines the supported tools, interfaces and checks available to your AI agents.

Your PDKsYour design dataYour review process

One platform.
Two deployment options.

Run Trame on your own hardware or choose Trame-managed infrastructure, with deployment and support tailored to your team.

ON YOUR HARDWARE

Local deployment

Deploy Trame on your own servers and workstations, connected to your existing EDA environment.

  • Your hardware and infrastructure
  • Local PDK AI-Agent for confidential technology data
  • Deployment tailored to your security and NDA requirements
  • Works with Trame EDA, Cadence, Synopsys and Siemens EDA tools
  • Training and support options for your team
Contact for more details about local deployment

ON TRAME INFRASTRUCTURE

Trame-managed deployment

A lower-cost way to adopt AI-driven design, without buying and maintaining dedicated AI hardware.

  • Works with Trame EDA, Cadence, Synopsys and Siemens EDA tools
  • Infrastructure provided and maintained by Trame
  • Guaranteed hardware resources for your agreed capacity
  • Support included
  • Resources and service scope tailored to your needs
Contact for more details about Trame-managed deployment

Contact us to discuss pricing, hardware capacity and support. EDA licences, PDK access, NDA requirements, model routing and data handling are agreed before deployment. Trame-managed infrastructure does not change the data-sharing permissions agreed for your PDK.

A FEW PRACTICAL DETAILS

Your team.
Your environment.

Do we need to use Trame EDA?

Trame connects AI-driven workflows to Cadence, Synopsys, Siemens EDA and Trame EDA tools, in either local or Trame-managed deployment. Supported products, versions and workflow steps are agreed for the project.

How do you handle PDK confidentiality and NDAs?

The local PDK architecture keeps technology-aware processing in your authorised environment. A communication gateway governs sharing of approved requests and abstract results with global orchestration. Model routing, access controls and disclosure policies are configured against your foundry NDA and licence terms before deployment. See the architecture.

What do engineers remain responsible for?

Requirements, architectural decisions, acceptance criteria, result review and release approval. Agent work is checked through the engineering workflow.

How can we deploy Trame?

Choose local deployment on your own hardware, with training and support options, or Trame-managed infrastructure with guaranteed resources for the agreed capacity and included support. Contact us for pricing and the appropriate scope.

LET’S MAKE IT CONCRETE

Equip your team
with Trame.

Discuss your deployment, EDA integration and support requirements.

Discuss your project