01 / FULL CHIP
Bring the blocks together.

PDK, IP integration, pad ring, sign-off and GDSII stream-out.
TRAME / AI-DRIVEN IC DESIGN
Trame combines advanced AI reasoning with specialised local AI agents for IC design, simulation and verification—with engineers in control.
Local agents protect foundry PDKs and your circuit designs. How it works
01 / FULL CHIP

PDK, IP integration, pad ring, sign-off and GDSII stream-out.
02 / SAR ADC

Specification, schematic, layout and post-layout verification.
Based on the published case studies.
HOW TRAME WORKS
Specialised local AI agents develop circuits, analyse the PDK and run design iterations. Trame AI-Agent coordinates the workflow; engineers set requirements and approve decisions.
Specifications, technology and rules.
Circuits, models and testbenches.
Layout, routing and integration.
Simulation, PVT, Monte Carlo and PEX.
Verification closure and engineer-approved release.
LOCAL AI-AGENTS
Local agents protect foundry-owned PDKs and your circuit designs within your authorised environment.
The PDK AI-Agent and circuit design run locally, supporting foundry NDA and design confidentiality requirements.
Requests
Approved abstract results
Access control · Disclosure policies
PDK analysis · Circuit design
Simulation analysis · Optimisation
SPICE · Synthesis · Layout
DRC · LVS · PEX
Models · Libraries
Design rules
DESIGNED WITH TRAME

Analog building block
A wide-swing cascode mirror distributing matched 10-µA currents, redesigned and checked for each process.
Evidence Layout & simulation · Verification scope ↗
Explore this circuit
Analog building block
A switched-current ΔVBE sensor across bulk CMOS, FD-SOI and FinFET, with signed-off layouts and complete temperature, noise and Monte Carlo characterization.
Evidence Layout & simulation · Verification scope ↗
Explore this circuit
Laser-capture front end
Three sensing paths with programmable transimpedance gain, matched response and on-chip electrical calibration.
Evidence Layout & simulation · Verification scope ↗
Explore this circuitExplore physical layouts, simulation curves and verification scope. Each design includes its simulation conditions and verification status.
WORK WITH THE TOOLS YOU USE
Trame EDA. Cadence. Synopsys. Siemens EDA.
Supported products, versions, interfaces and workflow stages are agreed for your project.
Design, simulation and verification in your licensed Cadence environment.
AI-driven design and verification within your Synopsys workflow.
Design and verification using your Siemens EDA environment.
Circuit, flow and result management within the developing Trame EDA platform.
Run Trame on your hardware or let us manage the infrastructure.
Keep Trame within your existing environment.
Infrastructure operated and maintained by Trame.
Both options follow your foundry NDA, licence and design-confidentiality requirements. Only approved requests and abstract results may be shared.
How local agents protect your dataLET’S MAKE IT CONCRETE
Discuss your circuit, EDA environment and deployment requirements.