SELECTED WORK

Engineering,
in the details.

Circuit case studies from Raphael Viera’s published portfolio: physical layouts, simulation results and the verification scope behind each design.

SAiR10 ADC layouts for 65 nm CMOS, 16 nm FinFET and 22 nm FD-SOI, shown at a common scale

DATA CONVERSION

One ADC. Three technologies.

A 10-bit, 5-MS/s asynchronous SAR ADC developed from a common specification across bulk CMOS, FD-SOI and FinFET.

65 nm CMOS · 22 nm FD-SOI · 16 nm FinFET

Layout & extracted-simulation case study
Bias-generator layouts in three CMOS technologies

ANALOG BUILDING BLOCK

Precision in the details.

An eight-output bias generator distributing matched 10-µA currents, adapted and characterized for three process technologies.

Current distribution · Matching · Migration

Layout & simulation case study
PTAT temperature-sensor layouts compared at the same scale

SENSING

A temperature sensor, rethought.

A switched-current PTAT sensor explored across bulk CMOS, FD-SOI and FinFET, with temperature, noise and Monte Carlo characterization.

Temperature sensing · PVT · Statistics

Layout & simulation case study

Showing all 3 case studies.

These are design and simulation case studies. Technology coverage and verification scope are documented in each linked study; measured-silicon results are not implied.

MORE FROM THE PORTFOLIO

Follow the circuit
from idea to evidence.

Explore current references, clock-monitoring circuits and further design studies in the complete portfolio.

Open the full portfolio

LET’S MAKE IT CONCRETE

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engineering challenge?

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